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a
Dual RF/IF PLL Frequency Synthesizers ADF4210/ADF4211/ADF4212/ADF4213
GENERAL DESCRIPTION
FEATURES ADF4210: 550 MHz/1.2 GHz ADF4211: 550 MHz/2.0 GHz ADF4212: 1.0 GHz/2.7 GHz ADF4213: 1.0 GHz/3 GHz 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler RF and IF: 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents 3-Wire Serial Interface Analog and Digital Lock Detect Fastlock Mode Power-Down Mode
The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B Counters and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (PhaseLocked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface. APPLICATIONS The devices operate with a power supply ranging from 2.7 V to Base Stations for Wireless Radio (GSM, PCS, DCS, 5 V and can be powered down when not in use. CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VP1 VP2 RSET
12-BIT IF B-COUNTER IFIN IF PRESCALER 8-BIT IF A-COUNTER
PHASE COMPARATOR
REFERENCE
CHARGE PUMP IF CURRENT SETTING IFCP3 IFCP2 IFCP1
CPIF
REFIN
OSCILLATOR 14-BIT IF R-COUNTER
IF LOCK DETECT
CLOCK DATA LE
24-BIT DATA SDOUT REGISTER 14-BIT RF R-COUNTER
OUTPUT MUX
MUXOUT
RFCP3 RFCP2 RFCP1 RF LOCK DETECT IF CURRENT SETTING CHARGE PUMP PHASE COMPARATOR REFERENCE RSET FLO SWITCH FLO
12-BIT RF B-COUNTER RFIN RF PRESCALER 6-BIT RF A-COUNTER
CPRF
ADF4210/ADF4211/ ADF4212/ADF4213
AGNDIF
DGNDRF
AGNDRF
DGNDIF
DGNDIF
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
ADF4210/ADF4211/ADF4212/ADF4213-SPECIFICATIONS1
(VDD1 = VDD2 = 3 V 10%, 5 V 10%; VDD1, VDD2 VP1, VP2 6.0 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; RSET = 2.7 k TA = TMIN to TMAX unless otherwise noted.)
Parameter
RF/IF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) ADF4210 ADF4211 ADF4212 ADF4213 RF Input Sensitivity IF Input Frequency (IFIN) ADF4210 ADF4211 ADF4212 ADF4213 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 RF/IF CHARACTERISTICS (5 V) RF Input Frequency (RFIN) ADF4210 ADF4211 ADF4212 ADF4213 RF Input Sensitivity IF Input Frequency (IFIN) ADF4210 ADF4211 ADF4212 ADF4213 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage B Version B Chips2 Unit Test Conditions/Comments See Figure 3 for Input Circuit. Use a square wave for frequencies lower than FMIN.
dBm to 50
;
0.1/1.2 0.1/2.0 0.15/2.7 0.2/3.0 -10/0 60/550 60/550 0.06/1.0 0.06/1.0 -10/0 165
0.1/1.2 0.1/2.0 0.15/2.7 0.2/3.0 -10/0 60/550 60/550 0.06/1.0 0.06/1.0 -10/0 165
GHz min/max GHz min/max GHz min/max GHz min/max dBm min/max MHz min/max MHz min/max GHz min/max GHz min/max dBm min/max MHz max
0.18/1.2 0.18/2.0 0.2/2.3 0.2/2.5 -5/0 100/550 100/550 0.1/1.0 0.1/1.0 -5/0 200 0/115 -5/0 10 100 55
0.18/1.2 0.18/2.0 0.2/2.3 0.2/2.5 -5/0 100/550 100/550 0.1/1.0 0.1/1.0 -5/0 200 0/115 -5/0 10 100 55
GHz min/max GHz min/max GHz min/max GHz min/max dBm min/max MHz min/max MHz min/max GHz min/max GHz min/max dBm min/max MHz max MHz min/max dBm min/max pF max A max MHz max
See Figure 3 for Input Circuit. Use a square wave for frequencies lower than FMIN.
See Figure 2 for Input Circuit. For F < 5 MHz, use dc-coupled square wave (0 to VDD ). AC-Coupled. When dc-coupled, 0 to VDD max (CMOS-Compatible)
5 625 3 1.5/5.6 1 2 2 2 0.8 x DVDD 0.2 x DVDD 1 10 DVDD - 0.4 0.4
5 625 3 1.5/5.6 1 2 2 2 0.8 x DVDD 0.2 x DVDD 1 10 DVDD - 0.4 0.4
mA typ A typ % typ k, min/max nA typ % typ % typ % typ V min V max A max pF max V min V max
Programmable: See Table V With RSET = 2.7 k With RSET = 2.7 k
0.5 V VCP 0.5 V VCP VCP = VP /2
VP - 0.5 V VP - 0.5 V
IOH = 500 A IOL = 500 A
-2-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
Parameter
POWER SUPPLIES VDD1 VDD2 VP IDD (RF + IF)6 ADF4210 ADF4211 ADF4212 ADF4213 IDD (RF Only) ADF4210 ADF4211 ADF4212 ADF4213 IDD (IF Only) ADF4210 ADF4211 ADF4212 ADF4213 IP (IP1 + IP2) Low-Power Sleep Mode NOISE CHARACTERISTICS ADF4213 Phase Noise Floor7 Phase Noise Performance8 ADF4210/ADF4211, IF: 540 MHz Output9 ADF4212/ADF4213, IF: 900 MHz Output10 ADF4210/ADF4211, RF: 900 MHz Output10 ADF4212/ADF4213, RF: 900 MHz Output10 ADF4211/ADF4212, RF: 1750 MHz Output12 ADF4211/ADF4212, RF: 1750 MHz Output13 ADF4212/ADF4213, RF: 2400 MHz Output14 Spurious Signals ADF4210/ADF4211, IF: 540 MHz Output9 ADF4212/ADF4213, IF: 900 MHz Output10 ADF4210/ADF4211, RF: 900 MHz Output10 ADF4212/ADF4213, RF: 900 MHz Output10 ADF4211/ADF4212, RF: 1750 MHz Output12 ADF4211/ADF4212, RF: 1750 MHz Output13 ADF4212/ADF4213, RF: 2400 MHz Output14
B Version B Chips2 Unit
2.7/5.5 VDD1 VDD1/6.0 11.5 15.0 17.5 20 6.75 10 12.5 15 5.5 5.5 5.5 5.5 1.0 1 -171 -164 -91 -89 -89 -91 -85 -67 -88 -88/-90 -90/-94 -90/-94 -90/-94 -80/-82 -65/-70 -80/-82 2.7/5.5 VDD1 VDD1/6.0 11.5 15.0 17.5 20 6.75 10 12.5 15 5.5 5.5 5.5 5.5 1.0 1 -171 -164 -91 -89 -89 -91 -85 -67 -88 -88/-90 -90/-94 -90/-94 -90/-94 -80/-82 -65/-70 -80/-82 V min/V max V min/V max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max A typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ
Test Conditions/Comments
VDD1, VDD2
VDD1, VDD2
6.0 V
9.0 mA typical 11.0 mA typical 13.0 mA typical 15 mA typical 5.0 mA typical 7.0 mA typical 9.0 mA typical 11 mA typical 4.5 mA typical 4.5 mA typical 4.5 mA typical 4.5 mA typical TA = 25C, 0.55 mA typical
@ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency See Note 11 See Note 11 See Note 11 See Note 11 @ 200 Hz Offset and 10 kHz PFD Frequency @ 1 kHz Offset and 1 MHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency See Note 11 See Note 11 See Note 11 See Note 11 @ 10 kHz/20 kHz and 10 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C. 2 The B Chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is less than this value. 4 VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels, TA = 25C. 5 Guaranteed by design. Sample tested to ensure compliance. 6 VDD = 3 V; P = 16; RFIN = 900 MHz; IFIN = 540 MHz, TA = 25C. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See TPC 16. 8 The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 9 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 11 Same conditions as listed in Note 10. 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. 14 fREFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz. Specifications subject to change without notice.
REV. A
-3-
ADF4210/ADF4211/ADF4212/ADF4213 (V 1 = V 2 = 3 V 10%, 5 V TIMING CHARACTERISTICS = AGND = DGND = 0 V; T = T
DD DD IF IF A
MIN
10%; VDD1, VDD2 VP1, VP2 6 V to TMAX unless otherwise noted.)
10%; AGNDRF = DGNDRF
Parameter t1 t2 t3 t4 t5 t6
Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK Set-Up Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Set-Up Time LE Pulsewidth
NOTES Guaranteed by design but not production tested. Specifications subject to change without notice.
t3
CLOCK
t4
t1
DATA DB20 (MSB) DB19
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C unless otherwise noted)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . -0.3 V to VP + 0.3 V REFIN, RFINA, RFINB, IFINA, IFINB to GND . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4C/W CSP JA (Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122C/W
CSP JA (Paddle Not Soldered) . . . . . . . . . . . . . . . . 216C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high-performance RF integrated circuit with an ESD rating of < 2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE
WARNING!
ESD SENSITIVE DEVICE
Model ADF4210BRU ADF4210BCP ADF4211BRU ADF4211BCP ADF4212BRU ADF4212BCP ADF4213BRU ADF4213BCP
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Thin Shrink Small Outline Package (TSSOP) Chip Scale Package Thin Shrink Small Outline Package (TSSOP) Chip Scale Package Thin Shrink Small Outline Package (TSSOP) Chip Scale Package Thin Shrink Small Outline Package (TSSOP) Chip Scale Package -4-
Package Option* RU-20 CP-20 RU-20 CP-20 RU-20 CP-20 RU-20 CP-20 REV. A
*Contact the factory for chip availability.
ADF4210/ADF4211/ADF4212/ADF4213
PIN FUNCTION DESCRIPTIONS Pin Number TSSOP 1 Mnemonic VDD1 Function Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. V DD1 should have a value of between 2.7 V and 5.5 V. V DD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to V DD1. In systems where VDD1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V. Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input to an external VCO. Ground Pin for the RF Digital Circuitry. Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO. Ground Pin for the RF Analog Circuitry. RF/IF Fastlock Mode. Reference Input. This is a CMOS input with a nominal threshold of V DD/2 and an equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator. Digital Ground for the IF Digital, Interface and Control Circuitry. This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled Reference Frequency to be accessed externally. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between I CP and RSET is 13.5 ICP MAX = RSET So, with RSET = 2.7 k, ICP MAX = 5 mA for both the RF and IF Charge Pumps. Ground Pin for the IF Analog Circuitry. Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO. Ground Pin for the IF Digital, Interface, and Control Circuitry. Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input to an external VCO. Power Supply for the IF Charge Pump. This should be greater than or equal to V DD2. In systems where VDD2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V. Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. V DD2 should have a value of between 2.7 V and 5.5 V. VDD2 must have the same potential as V DD1.
2 3 4 5 6 7 8 9 10 11
V P1 CPRF DGNDRF RFIN AGNDRF FLO REFIN DGNDIF MUXOUT CLK
12 13 14
DATA LE RSET
15 16 17 18 19 20
AGNDIF IFIN DGNDIF CPIF V P2 VDD2
PIN CONFIGURATIONS TSSOP
VP1
CP-20
VDD1 VDD2 CPIF
16
15 DGNDIF 14 IFIN 13 AGNDIF 12 RSET 11 LE
VDD1 1 VP1 2 CPRF 3 DGNDRF 4 RFIN 5 AGNDRF 6
20 19
VDD2 VP2 CPIF DGNDIF IFIN
CPRF 1 DGNDRF 2 RFIN 3 AGNDRF FLO
4 5
20
19
18 17
ADF4210/ ADF4211/ ADF4212/ ADF4213
18 17 16
ADF4210/ ADF4211/ ADF4212/ ADF4213
TOP VIEW (Not to Scale)
6 7 8 9 10
TOP VIEW 15 AGNDIF (Not to Scale) 14 RSET FLO 7
13 12 11
REFIN 8 DGNDIF 9 MUXOUT 10
LE DATA CLK
REFIN
CLK
VP2
DGNDIF
REV. A
-5-
MUXOUT
DATA
ADF4210/ADF4211/ADF4212/ADF4213-Typical Performance Characteristics
0
FREQUENCY 50000000.0 150000000.0 250000000.0 350000000.0 450000000.0 550000000.0 650000000.0 750000000.0 850000000.0 950000000.0 1050000000.0 1150000000.0 1250000000.0 1350000000.0 1450000000.0 1550000000.0 1650000000.0 1750000000.0 1850000000.0 1950000000.0 2050000000.0 S11 REAL 0.955683 0.956993 0.935463 0.919706 0.871631 0.838141 0.799005 0.749065 0.706770 0.671007 0.630673 0.584013 0.537311 0.505090 0.459446 0.381234 0.363150 0.330545 0.264232 0.242065 0.181238 S11 IMAG -0.052267 -0.112191 -0.185212 -0.252576 -0.323799 -0.350455 -0.408344 -0.455840 -0.471011 -0.535268 -0.557699 -0.604256 -0.622297 -0.642019 -0.686409 -0.693908 -0.679602 -0.721812 -0.697386 -0.711716 -0.723232 FREQUENCY 2150000000.0 2250000000.0 2350000000.0 2450000000.0 2550000000.0 2650000000.0 2750000000.0 2850000000.0 2950000000.0 S11 REAL 0.138086 0.102483 0.054916 0.018475 -0.019935 -0.054445 -0.083716 -0.129543 -0.154974 S11 IMAG
-5
RF INPUT POWER - dBm
-0.699896 -0.704160 -0.696325 -0.669617 -0.668056 -0.666995 -0.634725 -0.615246 -0.610398
VDD = 3V VP = 3V
-10 TA = +85 C -15 TA = +25 C -20 TA = -40 C
-25 -30
-35 0 1 2 3 RF INPUT FREQUENCY - GHz
TPC 1. S-Parameter Data for the ADF4213 RF Input (Up to 3.0 GHz)
TPC 4. Input Sensitivity (ADF4213)
0 -10 -20 REFERENCE LEVEL = -5.2dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz -40 -50 -60 -70 -91.2dBc/Hz -80 -90 -100 -2kHz -1kHz 900MHz +1kHz +2kHz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 19
10dB/DIVISION -40 -50
RL = -40dBc/Hz
RMS NOISE = 0.5421
0.54 rms -60
PHASE NOISE - dBc/Hz
OUTPUT POWER - dB
-30
-70 -80 -90 -100 -110 -120 -130 -140 100Hz
1kHz 10kHz 100kHz FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TPC 2. ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)
TPC 5. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 s)
10dB/DIVISION -40 -50
RL = -40dBc/Hz
RMS NOISE = 0.6522
0 -10
0.65 rms
REFERENCE LEVEL = -5.7dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 4.2 SECONDS AVERAGES = 20
-60
PHASE NOISE - dBc/Hz
-20
OUTPUT POWER - dB
-70 -80 -90 -100 -110 -120 -130 -140 100Hz
-30 -40 -50 -60 -70 -80 -90 -100
-91.0dBc/Hz
1kHz 10kHz 100kHz FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
-400kHz
-200kHz
900MHz
200kHz
400kHz
TPC 3. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 s)
TPC 6. ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)
-6-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
0 -10 -20
OUTPUT POWER - dB
0
REFERENCE LEVEL = -5.7dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 35kHz OUTPUT POWER - dB RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 4.2 SECONDS AVERAGES = 25 -10 -20 -30 -40 -50 -60 -70 -80 -90
REFERENCE LEVEL = -8.0dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 10
-30 -40 -50 -60 -70
-90.5dBc/Hz -80 -90 -100 -400kHz -200kHz 900MHz +200kHz +400kHz -75.2dBc/Hz
-100 -400Hz -200Hz 1750MHz +200Hz +400Hz
TPC 7. ADF4213 Reference Spurs (900 MHz, 200 kHz, 35 kHz)
TPC 10. ADF4213 Phase Noise (1750 MHz, 30 kHz, 3 kHz)
10dB/DIVISION -40 -50 -60
PHASE NOISE - dBc/Hz
RL = -40dBc/Hz
RMS NOISE = 1.6
0 -10 -20
POWER OUTPUT - dB
REFERENCE LEVEL = -5.7dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 3Hz VIDEO BANDWIDTH = 3Hz SWEEP = 255 SECONDS POSITIVE PEAK DETECT MODE -79.6dBc
-70 1.6 rms -80 -90 -100 -110 -120 -130 -140 100Hz
-30 -40 -50 -60 -70 -80 -90
FREQUENCY OFFSET FROM 1750MHz CARRIER
1MHz
-100 -80kHz -40kHz 1750MHz +40kHz +80kHz
TPC 8. ADF4213 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz)
TPC 11. ADF4213 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)
10dB/DIVISION -40 -50 -60 1.7 rms RL = -40dBc/Hz RMS NOISE = 1.7
0 -10 -20
OUTPUT POWER - dB
REFERENCE LEVEL = -4.2dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz
-30 -40 -50 -60
PHASE NOISE - dBc/Hz
RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 45 -86.6dBc/Hz
-70 -80 -90 -100 -110 -120 -130
-70 -80 -90 -100 -2kHz -1kHz 3100MHz +1kHz +2kHz
-140 100Hz
FREQUENCY OFFSET FROM 3100MHz CARRIER
1MHz
TPC 9. ADF4213 Phase Noise (2800 MHz, 1 MHz, 100 kHz)
TPC 12. ADF4213 Integrated Phase Noise (2800 MHz, 1 MHz, 100 kHz)
REV. A
-7-
ADF4210/ADF4211/ADF4212/ADF4213
0 -10 -20 OUTPUT POWER - dB -30 -40 -50 -60 -70 -80 -90 -100 -2MHz -1MHz 3100MHz +1MHz +2MHz
-180 1 10 100 1000 PHASE DETECTOR FREQUENCY - kHz 10000 -120
REFERENCE LEVEL = -17.2dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 13 SECONDS AVERAGES = 1 PHASE NOISE - dBc/Hz LOOP BANDWIDTH = 100kHz
-130
VDD = 3V VP = 5V
-140
-150
-80.6dBc
-160
-170
TPC 13. ADF4213 Reference Spurs (2800 MHz, 1 MHz, 100 kHz)
TPC 16. ADF4213 Phase Noise (Referred to CP Output) vs. PFD Frequency
-60 VDD = 3V VP = 3V
PHASE NOISE - dBc/Hz
-60 VDD = 3V VP = 5V -70
-70
-80
FIRST REFERENCE SPUR - dBc
-80
-90
-90
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 14. ADF4213 Phase Noise vs. Temperature (900 MHz, 200 kHz, 20 kHz)
TPC 17. ADF4213 Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz)
-5 -15
FIRST REFERENCE SPUR - dBc
-60
-25 -35 -45 -55 -65 -75 -85 -95 -105 0 1 2 3 TUNING VOLTAGE - Volts
VDD = 3V VP = 5V
PHASE NOISE - dBc/Hz
-70
VDD = 3V VP = 5V
-80
-90
4
5
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 15. ADF4213 Reference Spurs (200 kHz) vs. V TUNE (900 MHz, 200 kHz, 20 kHz)
TPC 18. ADF4213 Phase Noise vs. Temperature (836 MHz, 30 kHz, 3 kHz)
-8-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
-60 VDD = 3V VP = 5V -70
PRESCALER (P/P + 1)
FIRST REFERENCE SPUR - dBc
-80
The dual modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = PB + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF/IF input stage and divides it down to a manageable frequency for the CMOS A and B counters in the RF and If sections. The prescaler in both sections is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. See Tables IV and VI. It is based on a synchronous 4/5 core.
RF/IF A AND B COUNTERS
-90
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 19. ADF4213 Reference Spurs vs. Temperature (836 MHz, 30 kHz, 3 kHz)
The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less, when VDD = 5 V. Typically, they will work with 250 MHz output from the prescaler. Thus, with an RF input frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid.
Pulse Swallow Function
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL NC REFIN NC SW1 SW3 NO NC = NO CONNECT 100k TO R COUNTER BUFFER
The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P x B) + A] x fREFIN/R fVCO = Output Frequency of external voltage controlled oscillator (VCO). P B A = Preset modulus of dual modulus prescaler (8/9, 16/17, etc.). = Preset Divide Ratio of binary 13-bit counter (3 to 8191). = Preset Divide Ratio of binary 6-bit A counter (0 to 63). = Preset divide ratio of binary 15-bit programmable reference counter (1 to 32767).
SW2
fREFIN = External reference frequency oscillator.
Figure 2. Reference Input Stage
RF/IF INPUT STAGE
R
The RF/IF input stage is shown in Figure 3. It is followed by a 2-stage limiting amplifier to generate the CML (Current Mode Logic) clock levels needed for the prescaler.
BIAS GENERATOR 2k RFINA RFINB 1.6V AVDD 2k
N = BP + A
13-BIT BCOUNTER LOAD LOAD 5-BIT ACOUNTER
TO PFD
FROM RF INPUT STAGE
PRESCALER P/P + 1 MODULUS CONTROL
Figure 4. RF/IF A and B Counters
RF/IF COUNTER
AGND
Figure 3. RF/IF Input Stage
The 15-bit RF/IF R counter allows the input reference frequency to be divided down to product the input clock to the phase frequency detector (PFD). Division ratios from 1 to 32767 are allowed.
REV. A
-9-
ADF4210/ADF4211/ADF4212/ADF4213
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP Lock Detect
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The PFD includes a fixed-delay element that sets the width of the antibacklash pulse. This is typically 3 ns. This pulse ensures that there is no deadzone in the PFD transfer function and gives a consistent reference spur level.
VP CHARGE PUMP HI D1 U1 R DIVIDER CLR1 Q1 UP
MUXOUT can be programmed for two types of lock detect: Digital Lock Detect and Analog Lock Detect. Digital Lock Detect is active high. It is set high when the phase error on three consecutive Phase Detector cycles is less than 15 ns. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected, it is high with narrow low-going pulses.
RF/IF INPUT SHIFT REGISTER
DELAY
U3
CP
CLR2 HI D2 U2 N DIVIDER Q2
DOWN
The ADF421x family digital section includes a 24-bit input shift register, a 14-bit IF R counter and a 18-bit IF N counter, comprising a 6-bit IF A counter and a 12-bit IF B counter. Also present is a 14-bit RF R counter and an 18-bit RF N counter, comprising a 6-bit RF A counter and a 12-bit RF B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs DB1, DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table VI. Table I shows a summary of how the latches are programmed.
Table I. C2, C1 Truth Table
CPGND
R DIVIDER N DIVIDER
Control Bits C2 C1 0 0 1 1 0 1 0 1
Data Latch IF R Counter IF AB Counter (A and B) RF R Counter RF AB Counter (A and B)
CP OUTPUT
Figure 5. RF/IF PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF421x family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Tables III and V. Figure 6 shows the MUXOUT section in block diagram form.
DVDD
IF ANALOG LOCK DETECT IF R COUNTER OUTPUT IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT RF R COUNTER OUTPUT RF N COUNTER OUTPUT RF ANALOG LOCK DETECT DIGITAL LOCK DETECT
MUX
CONTROL
MUXOUT
DGND
Figure 6. MUXOUT Circuit
-10-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
Table II. ADF421x Family Latch Summary
IF R COUNTER LATCH
LOCK DETECT PRECISION THREE-STATE CP IF PD POLARITY IF FO
IF CP CURRENT SETTING
15-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 IF CP2 IF CP1 IF CP0 P4 P3 P2 P1 R15 R14
DB14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
IF N COUNTER LATCH
IF POWERDOWN IF CP GAIN
IF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 P8 P7 P6 P5 B12 B11 B10 B9 B8
DB14 B7
DB13 DB12 B6 B5
DB11 DB10 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
RF R COUNTER LATCH
RF LOCK DETECT THREE-STATE CP RF PD POLARITY RF FO
RF CP CURRENT SETTING
15-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 RF CP2 RF CP1 RF CP0 P12 P11 P10 P9 R15 R14
DB14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (1)
DB0 C1 (0)
RF N COUNTER LATCH
RF POWERDOWN RF CP GAIN
RF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 P17 P16 P15 P14 B12 B11 B10 B9 B8
DB14 B7
DB13 DB12 B6 B5
DB11 DB10 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (1)
DB0 C1 (1)
REV. A
-11-
ADF4210/ADF4211/ADF4212/ADF4213
Table III. IF R Counter Latch Map
IF R COUNTER LATCH
LOCK DETECT PRECISION THREE-STATE CP IF PD POLARITY
IF FO
IF CP CURRENT SETTING
15-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 IF CP2 IF CP1
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 IF CP0 P4 P3 P2 P1 R15 R14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
R15 0 0 0 0 . . . 1 1 1 1
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 32764 32765 32766 32767
P1
0 1
IF PD POLARITY
NEGATIVE POSITIVE
P2 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 P11 FROM RF R LATCH 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
P4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
P3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH STATE RF REFERENCE DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE-STATE OUTPUT IF COUNTER RESET RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT RF COUNTER RESET IF AND RF COUNTER RESET
ICP (mA) IF CP2 0 0 0 0 1 1 1 1 IF CP1 0 0 1 1 0 0 1 1 IF CP0 0 1 0 1 0 1 0 1 1.5k 1.088 2.176 3.264 4.352 5.44 6.528 7.616 8.704 2.7k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 5.6k 0.294 0.588 0.882 1.176 1.47 1.764 2.058 2.352
-12-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
Table IV. IF N Counter Latch Map
IF N COUNTER LATCH
IF POWERDOWN IF CP GAIN
IF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 DB22 P8 P7
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P6 P5 B12 B11 B10 B9 B8 B7
DB13 DB12 B6 B5
DB11 DB10 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
P6 0 0 1 1
P5 0 1 0 1
IF PRESCALER 8/9 16/17 32/33 64/65
A6 0 0 0 0 . . . 1 1 1 1
A5 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
A2 0 1 1 0 . . . 0 0 1 1
A1 1 0 1 0 . . . 0 1 0 1
A COUNTER DIVIDE RATIO 1 2 3 4 . . . 60 61 62 63
P7 0 1
IF POWER-DOWN DISABLE ENABLE
B12 0 0 . . . 1 1 1 1
B11 0 0 . . . 1 1 1 1
B10 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 1 . . . 1 1 1 1
B2 1 0 . . . 0 0 1 1
B1 1 0 . . . 0 1 0 1
B COUNTER DIVIDE RATIO 3 4 . . . 4092 4093 4094 4095
P8 0 1
IF CP GAIN DISABLE ENABLE N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS VALUES OF N FREF, NMIN is (P2 - P).
REV. A
-13-
ADF4210/ADF4211/ADF4212/ADF4213
Table V. RF R Latch Map
RF R COUNTER LATCH
RF LOCK DETECT THREE-STATE CP RF PD POLARITY RF FO
RF CP CURRENT SETTING
15-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 RF CP2 RF CP1
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 RF CP0 P12 P11 P10 P9 R15 R14 R13
DB13 DB12 R12 R11
DB11 DB10 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (1)
DB0 C1 (0)
R15 0 0 0 0 . . . 1 1 1 1
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 32764 32765 32766 32767
P9 0 1
RF PD POLARITY NEGATIVE POSITIVE
P10 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
P11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FROM IF R LATCH P4 P3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT IF DIGITAL LOCK DETECT LOGIC HIGH STATE RF REFERENCE DIVIDER OUTPUT RF N DIVIDER OUTPUT THREE-STATE OUTPUT IF COUNTER RESET RF DIGITAL LOCK DETECT RF/IF DIGITAL LOCK DETECT RF COUNTER RESET IF AND RF COUNTER RESET
ICP (mA) RF CP2 0 0 0 0 1 1 1 1 RF CP1 0 0 1 1 0 0 1 1 RF CP0 0 1 0 1 0 1 0 1 1.5k 1.125 2.25 3.375 4.5 5.625 6.75 7.7875 9.0 2.7k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 5.6k 0.301 0.602 0.904 1.205 1.506 1.808 2.109 2.411
-14-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
Table VI. RF N Counter Latch Map
RF N COUNTER LATCH
RF POWERDOWN RF CP GAIN
RF PRESCALER
12-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 DB22 P17 P16
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 P15 P14 B12 B11 B10 B9 B8 B7
DB13 DB12 B6 B5
DB11 DB10 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (1)
DB0 C1 (1)
P15 0 0 1 1
P14 0 1 0 1
PRESCALER 8/9 16/17 32/33 64/65
A6 0 0 0 0 . . . 1 1 1 1
A5 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
A2 0 1 1 0 . . . 0 0 1 1
A1 1 0 1 0 . . . 0 1 0 1
A COUNTER DIVIDE RATIO 1 2 3 4 . . . 60 61 62 63
P16 0 1
RF POWER-DOWN DISABLE ENABLE
B12 0 0 . . . 1 1 1 1
B11 0 0 . . . 1 1 1 1
B10 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 1 . . . 1 1 1 1
B2 1 0 . . . 0 0 1 1
B1 1 0 . . . 0 1 0 1
B COUNTER DIVIDE RATIO 3 4 . . . 4092 4093 4094 4095
P17 0 1
RF CP GAIN DISABLE ENABLE
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS VALUES OF N FREF, NMIN is (P2 - P).
REV. A
-15-
ADF4210/ADF4211/ADF4212/ADF4213
PROGRAM MODES
IF SECTION
PROGRAMMABLE IF REFERENCE (R) COUNTER
Table III and Table V show how to set up the Program Modes in the ADF421x family. The following should be noted: 1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop is locked and either IF or RF Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses. When the IF/RF Analog Lock Detect is chosen, the locked condition is indicated only when both IF and RF loops are locked. 2. The IF Counter Reset mode resets the R and AB counters in the IF section and also puts the IF charge pump into threestate. The RF Counter Reset mode resets the R and AB counters in the RF section and also puts the RF charge pump into three-state. The IF and RF Counter Reset mode does both of the above. Upon removal of the reset bits, the AB counter resumes counting in close alignment with the R counter (maximum error is one prescaler output cycle). 3. The Fastlock mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF CP Gain in the RF Reference counter is set to one.
IF Power-Down
If control bits C2, C1 are 0, 0, the data is transferred from the input shift register to the 14-bit IFR counter. Table III shows the input shift register data format for the IFR counter and the divide ratios possible.
IF Phase Detector Polarity
P1 sets the IF Phase Detector Polarity. When the IF VCO characteristics are positive this should be set to "1." When they are negative it should be set to "0." See Table III.
IF Charge Pump Three-State
P2 puts the IF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table III.
IF PROGRAM MODES
Table III and Table V show how to set up the Program Modes in the ADF421x family.
IF Charge Pump Currents
IFCP2, IFCP1, IFCP0 program current setting for the IF charge pump. See Table III.
PROGRAMMABLE IF AB COUNTER
It is possible to program the ADF421x family for either synchronous or asynchronous power-down on either the IF or RF side.
Synchronous IF Power-Down
Programming a "1" to P7 of the ADF421x family will initiate a power-down. If P2 of the ADF421x family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into threestate and then complete the power-down.
Asynchronous IF Power-Down
If control bits C2, C1 are 0, 1, the data in the input register is used to program the IF AB counter. The N counter consists of a 6-bit swallow counter (A counter) and 12-bit programmable counter (B counter). Table IV shows the input register data format for programming the IF AB counter and the possible divide ratios.
IF Prescaler Value
P5 and P6 in the IF A, B Counter Latch sets the IF prescaler value. See Table IV.
IF Power-Down
If P2 of the ADF421x family has been set to "1" (three-state the IF charge pump), and P7 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the IF power-down bit (P7).
Synchronous RF Power-Down
Table III and Table V show the power-down bits in the ADF421x family.
IF Fastlock
Programming a "1" to P16 of the ADF421x family will initiate a power-down. If P10 of the ADF421x family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into three-state and then complete the power-down.
Asynchronous RF Power-Down
The IF CP Gain bit (P8) of the IF N register in the ADF421x family is the Fastlock Enable Bit. Only when this is "1" is IF Fastlock enabled. When Fastlock is enabled, the IF CP current is set to its maximum value. Since the IF CP Gain bit is contained in the IF N Counter, only one write is needed to both program a new output frequency and also initiate Fastlock. To come out of Fastlock, the IF CP Gain bit on the IF N register must be set to "0." See Table IV.
If P10 of the ADF421x family has been set to "1" (three-state the RF charge pump), and P16 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power down on the rising edge of LE, which latches the "1" to the RF power-down bit (P16). Activation of either synchronous or asynchronous power-down forces the IF/RF loop's R and AB dividers to their load state conditions and the IF/RF input section is debiased to a highimpedance state. The REFIN oscillator circuit is only disabled if both the IF and RF power-downs are set. The input register and latches remain active and are capable of loading and latching data during all the power-down modes. The IF/RF section of the devices will return to normal powered up operation immediately upon LE latching a "0" to the appropriate power-down bit.
RF SECTION
PROGRAMMABLE RF REFERENCE (R) COUNTER
If control bits C2, C1 are 1, 0, the data is transferred from the input shift register to the 14-bit RFR counter. Table V shows the input shift register data format for the RFR counter and the possible divide ratios.
RF Phase Detector Polarity
P9 sets the IF Phase Detector Polarity. When the RF VCO characteristics are positive this should be set to "1." When they are negative it should be set to "0." See Table V.
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table V.
-16-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
RF PROGRAM MODES
Table III and Table V show how to set up the Program Modes in the ADF421x family.
RF Charge Pump Currents
APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver
RFCP2, RFCP1, RFCP0 program current setting for the RF charge pump. See Table V.
PROGRAMMABLE RF N COUNTER
Figure 7 shows the ADF4210/ADF4211/ADF4212/ADF4213 being used with a VCO to produce the LO for a GSM base station transmitter. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 . A typical GSM system would have a 13 MHz TCXO driving the reference input without any 50 termination. In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference.
WIDEBAND PLL
If control bits C2, C1 are 1, 1, the data in the input register is used to program the RF N (A + B) counter. The N counter consists of a 6-bit swallow counter (A Counter) and 12-bit programmable counter (B Counter). Table IV shows the input register data format for programming the RF N counter and the possible divide ratios.
RF Prescaler Value
P14 and P15 in the RF A, B Counter Latch sets the RF prescaler value. See Table VI.
RF Power-Down
Table III and Table V show the power-down bits in the ADF421x family.
RF Fastlock
The RF CP Gain bit (P17) of the RF N register in the ADF421x family is the Fastlock Enable Bit. Only when this is "1" is IF Fastlock enabled. When Fastlock is enabled, the RF CP current is set to its maximum value. Also an extra loop filter damping resistor to ground is switched in using the FL O pin, thus compensating for the change in loop characteristics while in Fastlock. Since the RF CP Gain bit is contained in the RF N Counter, only one write is needed to both program a new output frequency and also initiate Fastlock. To come out of Fastlock, the RF CP Gain bit on the RF N register must be set to "0." See Table VI.
IFOUT VP 100pF 18 18 18 100pF VCC VCO190620pF 540T 3.3k CPIF 5.6k 8.2nF RSET 2.7k 100pF 1.3nF VP2 VDD
Many of the wireless applications for synthesizers and VCOs in PLLs are narrowband in nature. These applications include various wireless standards such as GSM, DSC1800, CDMA, or WCDMA. In each of these cases, the total tuning range for the local oscillator is less than 100 MHz. However, there are also wideband applications where the local oscillator could have up to an octave tuning range. For example, cable TV tuners have a total range of about 400 MHz. Figure 8 shows an application where the ADF4213 is used to control and program the Micronetics M3500-1324. The loop filter was designed for an RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP multiplied by the gain factor of 4), VCO KD of 80 MHz/V (sensitivity of the M3500-1324 at an output of 2100 MHz) and a phase margin of 45C. In narrowband applications, there is generally a small variation (less than 10%) in output frequency and also a small variation (typically < 10%) in VCO sensitivity over the range. However,
RFOUT VP 100pF VDD2 VDD1 REFIN VP1 3.3k CPRF 1.3nF 5.6k 8.2nF 620pF 18 VCC 18
VCO190- 100pF 18 902T
ADF4210/ ADF4211/ ADF4212/ ADF4213
MUXOUT RFIN
LOCK DETECT 100pF
DGNDRF
AGNDRF
DGNDIF
51
DECOUPLING CAPACITORS (22 F/10PF) ON VDD, VP OF THE ADF4211/ADF4212/ADF4213 AND ON VCC OF THE VCOS HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4210/ADF4211/ADF4212/ADF4213
REV. A
-17-
SPI-COMPATIBLE SERIAL BUS
FREFIN
RFINB
AGNDIF
51
1000pF 1000pF
CLK DATA LE
51
ADF4210/ADF4211/ADF4212/ADF4213
20V VDD VP 1k 1000pF 1000pF FREFIN 51 CE CLK DATA LE MUXOUT RFIN VDD1 VDD2 VP1 VP2 REFIN CPRF RSET 3.9nF 2.7k 27nF 470 130pF 20k AD820 3k VCC V_TUNE OUT 18 12V 100pF 100pF 18 RFOUT
18
M3500-1324 GND
SPI-COMPATIBLE SERIAL BUS
LOCK DETECT 100pF
ADF4213
DGNDRF AGNDRF DGNDIF AGNDIF
51 DECOUPLING CAPACITORS ON VDD, VP OF THE ADF4213, ON VCC OF THE AD820 AND ON THE VCC OF THE M3500-1324 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO SIMPLIFY THE SCHEMATIC.
Figure 8. Wideband PLL Circuit
in wide-band applications both of these parameters have a much greater variation. In Figure 8, for example, we have -25% and +30% variation in the RF output from the nominal 1.8 GHz. The sensitivity of the VCO can vary from 130 MHz/V at 1900 MHz to 30 MHz/V at 2400 MHz. Variations in these parameters will change the loop bandwidth. This in turn can affect stability and lock time. By changing the programmable ICP, it is possible to obtain compensation for these varying loop conditions and ensure that the loop is always operating close to optimal conditions.
INTERFACING
When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be about 180 kHz.
SCLOCK MOSI SCLK SDATA LE CE
ADuC812
I/O PORTS
ADF4210/ ADF4211/ ADF4212/ ADF4213
The ADF4210/ADF4211/ADF4212/ADF4213 family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz, or one update every 1.1 ms. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds.
ADuC812 to ADF421x Family Interface
MUXOUT (LOCK DETECT)
Figure 9. ADuC812 to ADF421x Family Interface
ADSP-21xx to ADF421x Family Interface
Figure 9 shows the interface between the ADF421x family and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF421x family needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF421x family, it needs four writes (one each to the R counter latch and the AB counter latch for both RF1 and RF2 sides) for the output to become active.
Figure 10 shows the interface between the ADF421x family and the ADSP-21xx Digital Signal Processor. As previously discussed, the ADF421x family needs a 24-bit serial word for each latch write. The easiest way to accomplish this, using the ADSP-21xx family, is to use the Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the Autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
SCLK DT SCLK SDATA LE CE I/O FLAGS
ADSP-21xx
TFS
ADF4210/ ADF4211/ ADF4212/ ADF4213
MUXOUT (LOCK DETECT)
Figure 10. ADSP-21xx to ADF421x Family Interface
-18-
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
PCB Guidelines for Chip Scale Package
The lands on the chip scale package (CP-20), are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This will ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be clearance of at least 0.25 mm between the thermal pad and inner edges of the pad pattern. This will ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm grid pitch. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board pad to AGND.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Thin Shrink Small Outline Package (TSSOP) (RU-20)
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
Chip Scale Package (CP-20)
0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 16 0.009 (0.24) 15 0.148 (3.75) BSC SQ 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.030 (0.75) 0.022 (0.60) 0.014 (0.50)
0.157 (4.0) BSC SQ
0.010 (0.25) MIN
20 1
PIN 1 INDICATOR
TOP VIEW
BOTTOM VIEW
11 10 6 5
0.080 (2.25) 0.083 (2.10) SQ 0.077 (1.95)
12 MAX 0.035 (0.90) MAX 0.033 (0.85) NOM SEATING PLANE 0.020 (0.50) BSC
0.031 (0.80) MAX 0.026 (0.65) NOM
0.080 (2.00) REF
0.008 (0.20) REF
0.002 (0.05) 0.0004 (0.01) 0.0 (0.0)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. A
-19-
ADF4210/ADF4211/ADF4212/ADF4213-Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A. Changes to Test Conditions/Comments section of Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edit to RFIN and IFIN Function text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PCB Guidelines for Chip Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CP-20 Package replaced by CP-20[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
C01029-0-6/01(A) PRINTED IN U.S.A.
-20-
REV. A

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